Keynote Speeches

Dr. Joseph Sifakis | Prof. Radu Marculescu | Prof. Ping K. Ko | Prof. Patrick Yue

Dr. Joseph Sifakis
Verimag Laboratory, France

Keynote Speech Abstract:
Rigorous System Design

System design is the process leading from application software and a target platform to a mixed hardware/software system meeting given requirements. It radically differs from pure software design in that it must take into account not only functional but also extra-functional properties regarding the use of resources of the execution platform such as time, memory and energy.

We advocate for rigorous system design flows guaranteeing essential system properties. These should be

We present a rigorous system design flow based on the BIP component framework. The flow is fully automated and supported by a toolset including a compiler, the D-Finder compositional verification tool as well as model transformers.

Speaker Biography:

Joseph Sifakis is a CNRS researcher and the founder of Verimag laboratory in Grenoble, France. He studied Electrical Engineering at the Technical University of Athens and Computer Science at the University of Grenoble.

Joseph Sifakis is recognized for his pioneering work on both theoretical and practical aspects of Concurrent Systems Specification and Verification. He contributed to emergence of the area of model-checking, currently the most widely-used method for the verification of industrial applications. His current research activities include component-based design, modeling, and analysis of real-time systems with focus on correct-by-construction techniques.

Joseph Sifakis has received with Ed Clarke and Allen Emerson for their contribution to Model Checking, the Turing Award for 2007.

Prof. Radu Marculescu
Carnegie Mellon University, USA

Keynote Speech Abstract:
Design and Optimization of Thousand-core Systems

Continuous technology scaling allows hundreds and soon thousands of processing cores integrated on the same chip; this represents the multicore (or manycore) computing paradigm which makes it possible to run multiple heterogeneous applications concurrently on a single chip. However, on-chip power consumption represents one of the major bottlenecks in providing increased performance and enhanced capabilities for such platforms. Indeed, increased power consumption results not only in higher on-die temperature and reduced lifetime reliability, but also leads to faster discharge of battery-powered mobile devices.

In this talk we address some fundamental issues related to the design, evaluation, and hardware prototyping of scalable power and temperature management algorithms for next generation, massively parallel multicore systems. Starting from the existing solutions required to enable DVFS control at core-level, we focus our discussion on truly scalable system-level design methodologies that can take advantage of the existing knobs at circuit-level in order to optimize the dynamic power and thermal dissipation for systems consisting of thousands of cores.

Speaker Biography:

Radu Marculescu received his Ph.D. in Electrical Engineering from the University of Southern California, in 1998. He is currently a Professor in the Department of Electrical & Computer Engineering at Carnegie Mellon University. His current research focuses on developing design methodologies and software tools for system-on-chip design, on-chip communication, and cyber-physical systems. Dr. Marculescu has received the 2005 Transactions on Very Large Scale Integration Systems (T-VLSI) Best Paper Award, and Best Paper Awards from the Design Automation & Test in Europe (DATE) Conference and Asia & South Pacific Design Automation Conference (ASP-DAC). Dr. Marculescu serves as an Associate Editor of IEEE Transactions on Computers (T-COMP), IEEE Transactions on Computer-Aided Design (T-CAD), and ACM Transactions on Embedded Computing Systems (ACM TECS). Dr. Marculescu has been involved in organizing several international symposia, conferences, and workshops sponsored by professional organizations, as well as guest editor of Special Issues in archival journals and magazines.

Prof. Ping K. Ko

Prof. Patrick Yue

Keynote Speech Abstract:
The Evolution of Fabless IC Industry in China: Past, Present, and Future

The importance of China's role in the electronics industry, in terms of both market size and its criticality in global supply chain, cannot be overstated. On the industrial front, over the past decade, China has emerged from a mere service provider of semiconductor assembly and test to a significant player in both the foundry service and fabless IC design business. This paper will first provide a macro overview on the evolution of China's fabless IC industry. The key statistical figures and momentous milestones and events, during the 15-year history of China's fabless IC industry, will be reviewed. Next, several case studies will be presented to highlight the unique dynamics of building and running fabless IC companies in China. Finally, the authors will speculate on the most significant trends in technology development, business model and market segments for the fabless companies going into the next decade.

Speaker Biography (Prof. Ping K. Ko):

Prof. Ping K. Ko is a native of Hong Kong. He received his B.S. degree in Physics Hong Kong University in 1974, and M.S. and Ph.D. in Electrical Engineering and Computer Science (EECS) from the University of California at Berkeley, in 1978, and 1982 respectively. In 1982 and 1983, he was a Member of Technical Staff at Bell Laboratory. He joined the Berkeley faculty in 1984, and was Vice Chairman of the EECS department and Director of the Berkeley Microfabrication Laboratory before he returned to Hong Kong to the Hong Kong University of Science and Technology (HKUST) in August 1993, where he served as the Dean of Engineering from May 1994 to July 1999. In Hong Kong, he has been chairman of the Research Grants Council from 1993 to 2000, and a member of the University Grants Committee from 1993 to 1998. He was awarded the Justice of Peace in 1997.

At Berkeley, Professor Ko set up the Berkeley Device Research Group with his colleague Professor Chenming Hu, focusing on understanding the physics of MOS technology and devices, and developing CAD tools for the design of integrated circuits. Some notable results of this effort are the Berkeley Short-channel IGFET Models (BSIM's) and the Berkeley Reliability Tools (BERT), which are being used worldwide by IC design engineers. In particular, BSIM was established as an industry standard in 1996. For his contribution to the development of device models used for IC design, Professor Ko was awarded the 2002 IEEE Solid-State Circuits Award. Professor Ko holds six patents, and has authored or co-authored one book and over 200 research papers. He is a Fellow of the Institute of Electrical and Electronic Engineers (IEEE).

Since 2002, Professor Ko has been full-time as a VC focusing on fabless IC design companies in China. His current venture, Silicon Federation International (SFI), has provided funding for more than 10 companies.

Speaker Biography (Prof. Patrick Yue):

Prof. Patrick Yue (S'93-M'98-SM'05) was born in Nanjing, China in 1971 and lived in Hong Kong for ten years before moving to the US to study. He attained his B.S. degree in Electrical & Computer Engineering (ECE) at the University of Texas at Austin in 1992 with highest honor. He received his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1994 and 1998, respectively. He is currently a full Professor in Electrical and Computer Engineering Department at the University of California, Santa Barbara. Since July 2010, he has been on sabbatical leave to the Hong Kong University of Science and Technology as a Visiting Professor in ECE. His technical expertise is in the area of high-frequency modeling for transistor, passive components and IC packages; ESD protection devices and schemes for RFICs; CMOS wireless and wireline communication circuits; and CAD and design methodology for RFICs.

Based on his PhD work at Stanford, he co-founded Atheros Communications (now part of Qualcomm) where he was a member of the founding team that raised the first round of venture funding in 1998. He worked at Atheros for four years as an Analog Design Manager and the Foundry Manager. His knowhow in CMOS RF was one of the key technology differentiators for Atheros, which led to the volume production of the world's first CMOS 802.11 WiFi radio transceiver. In 2002, he joined a second startup Aeluros (now part of Netlogic Microsystems) to develop CMOS transceiver IC for 10-Gbit optical communications. He was responsible for handling the signal integrity issues at the chip, package and PCB interfaces. While working in the startups, Dr. Yue maintained his research activities by serving as a Consulting Assistant Professor at Stanford between 2001 and 2003. In 2003, after five years of industry experience, he returned to academia full time. He started teaching at Carnegie Mellon University in Pittsburgh, PA, as an Assistant Professor in ECE. In 2006, he moved back to CA to join UC Santa Barbara as an Associate Professor and later served as the Associate Director for the Computer Engineering Program. In 2010, he was promoted to a full professor.

Prof. Yue has contributed to more than 60 peer-reviewed technical papers and two book chapters in the field of RF device modeling and circuit design. He holds 13 US patents of which majority are employed in commercial products. He was a co-recipient of the 2003 International Solid-State Circuits Conference (ISSCC) Best Student Paper Award. He is the lead author of an all-time most cited paper in IEEE Journal of Solid-State Circuits on the invention of the patterned ground shield for on-chip inductors (Google Citation Index: 884). He has served on the committees for the IEEE Asian Solid-State Circuits Conference, IEEE Radio-Frequency IC Symposium, and Symposium on VLSI - Design, Automation and Test. He is an Editor of the IEEE Electron Device Letters covering the area of Integrated Circuits and ESD Protection. Prof. Yue was a member of the IEEE Electron Devices Society VLSI Technology and Circuits Committee between 2005 and 2010, and has been a Senior Member of IEEE since 2005.